The present invention relates to the interconnection and packaging of integrated circuits (ICs). More particularly, the present invention relates to the packaging of ICs on multichip modules.
As silicon device geometries shrink, IC densities and speed performance improve considerably. For example, some currently available ICs contain hundreds of thousands of gates per chip, and as many as 300 input/output pins (I/O). Systems with these devices switch in subnanosecond times. Further advances in chip densities and performance beyond these values are expected.
Conventional packaging and printed circuit board interconnection systems used to link these semiconductor devices to form processor systems and other circuits contain large numbers of interconnections, long signal paths and high capacitance materials. These characteristics introduce ground bounce, switching noise and propagation delays to the system. The impact of ground bounce, noise and propagation delays on the system increases in proportion to the number of chip I/Os and operating speed. Thus, as chip capabilities improve, circuit design can no longer be considered in isolation from packaging and interconnection design, since the packaging and interconnection hardware exact a performance penalty on the resulting systems.
To counter the limitations of commercially available, conventional packaging, designers of high-end computers frequently develop proprietary interconnection packages. Development of these packages is expensive and delays the time to market of the improved processor. However, as shown in FIG. 1, despite the efforts expended to develop proprietary packaging, system designers will encounter increasing difficulty in matching system speeds to bare chip speeds as improvements in IC technology continue. This performance gap 5 is represented in FIG. 1.
An approach to improving package performance and hence system speed is the multichip module. A multichip module is a collection of IC chips attached to a high density interconnect substrate that resembles and functions as a large, application-specific integrated circuit. A typical multichip module of the prior art is shown in U.S. Pat. No. 4,675,717 to Herrero et al. The module consists of a doped silicon substrate having power and ground planes. The doped substrate and the ground plane form one plate of a decoupling capacitor. The power plane forms the other plate of the capacitor. Above are the metal interconnect layers power and ground planes 14. The IC is either flip chip bonded to the metal interconnect layers or is secured using a bonding material and electrically connected to the metal interconnect layers using conventional wire bonding techniques. Other prior art modules include a layer of polyimide which serves as a dielectric between the metal interconnect layers.
Multichip modules of the types described above improve system performance in several ways. First, the capacitance of chip-to-chip interconnections is reduced by a factor of four over conventional packaging, thereby reducing signal propagation delays and power consumption. The shorter wire bonds reduce interconnect inductance and the resulting module serves to shorten signal delays over conventionally packaged systems. FIG. 2 illustrates the performance advantages achieved over conventional packaging by use of multichip modules. As is evident from the graph, the performance gap 30 inherent with multichip modules is significantly smaller than that incurred with conventional packaging.
Despite these performance improvements, the typical multichip module has several disadvantages that limit system performance, reduce yield and restrict the availability of multichip modules to a relatively small field of select users. Certain of these disadvantages stem from the use of polyimide and other organic materials as a dielectric. The raw material necessary to form the polyimide dielectric costs more than silicon-based materials and requires more processing steps to form the completed product. These characteristics of polyimide-dielectrics increase the cost of multichip modules and decrease the yield.
In addition, the mechanical properties of polyimide impose design constraints on the multichip system. Polyimides have poor thermal conductivity and a thermal expansion coefficient that differs from silicon based ICs. Polyimide structures therefore often require additional thermal metal pillars under the die to ensure adequate heat conduction and balanced thermal stresses. The area consumed by the pillars is unavailable as interconnect. Also, the polyimide dielectric is under tension after processing, and that tension, when coupled with metal film tension, results in a highly bowed, internally stressed structure. The bowed structure can cause module reliability problems. Finally, the polyimide has a tendency to absorb moisture. This characteristic can reduce part life and requires that special measures be taken to prevent corrosion.
Additional limitations on multichip module features arise from use of doped silicon as the module substrate. The doped silicon has a much higher current spreading resistance than a metal film. Furthermore, the requirement that the substrate be highly doped adds significantly to the module materials costs.